New materials and material compositions are being employed in industry in order to improve semiconductor devices such as transistors, for example. This allows one to improve the processing speed and performance of integrated circuits (ICs). A typical example is the deployment of a thin strained silicon film on top of a relaxed Silicon-Germanium (SiGe) buffer layer, on a Silicon (Si) substrate.
A conventional approach of using relaxed graded SiGe layers as buffers is now described. The concept of graded SiGe buffer layers was invented in 1991 by Fitzgerald et al. The results of their work are described in F. A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Michel, Y.-J Mii, and B. E. Weir, Appl. Phys. Lett., Vol. 59, p. 811, 1991. Such buffer layers are used as virtual substrates (VS) for applications in the area of high-speed electronics by means of metal-oxide semiconductor field-effect transistors (MOSFETs) and modulation-doped field-effect transistors (MODFETs) based on strained Si or Si1-xGex(0<x≦1). The active layers (e.g., Si) on top of a VS are strained because the VS has a lattice parameter intermediate between that of Si and Ge.
In the graded buffer approach, the Ge concentration x in a Si1-xGex alloy is raised in a linear or step-wise fashion from zero up to some final value xf.
In this way, dislocations are distributed in a larger volume compared to a SiGe film with constant composition, where they reside basically at the interface. As a result, threading dislocation (TD) arms become more mobile, long misfit segments are formed (ideally across the whole wafer) and the density of TDs piercing the active layers of devices, and spoiling their performance, is reduced.
To date, the highest low-temperature electron and hole mobilities in strained Si channels were reported in the following two papers: K. Ismail, M. Arafa, K. L. Saenger, J. O. Chu, and B. S. Meyerson, in Appl. Phys. Lett., Vol. 66, p. 1077, 1995; P. Weitz, R. J. Haug, K. Von Klitzing, and F. Schäffler, in Surf. Sci. 361/362, p. 542, 1996; and in strained Ge channels by H. von Känel, M. Kummer, G. Isella, E. Müller, and T. Hackbarth, in Appl. Phys. Lett., Vol. 80, p. 2922, 2002. This has been achieved using VS based on Fitzgerald's concept.
Conventional VS are, however, typically several microns thick because the grading rates have to be kept low (typically around 10%/μm) to assure low TD densities. Such VS are therefore very time consuming to fabricate with conventional growth techniques.
There does, however, exist a fast deposition process, called low-energy plasma-enhanced chemical vapor deposition (LEPECVD) by means of which time and material consumption has been minimized. The basic process, applied only to Si and SiGe films of a “quality sufficient for epitaxy”, is described and claimed in the US patent with patent number U.S. Pat. No. 6,454,855 B1, and in a pending PCT application published as WO 98/58099.
For the application of LEPECVD to p-MODFETs, a European patent application was filed on 22 Nov. 2001. Application number 01127834.8 was assigned. Subsequently, a PCT patent application was filed on 5 Sep. 2002 and the international application number PCT/EP 02/09922 was assigned. In the context of these applications 01127834.8 and PCT/EP 02/09922, the LEPECVD is used to grow thick graded relaxed SiGe layers. It is a disadvantage of thick graded SiGe buffer layers, that their thermal conductivity is relatively low. When using a substrate with such a thick SiGe buffer layer, heat dissipation might be a problem in particular in highly integrated circuits. If one uses a substrate with a thick SiGe buffer layer, the integration of Si circuits is difficult, since there are substantial differences in heights (large step heights) between the buffer and those areas where the buffer has been removed by means of etching. Photolithography on such a structured surface is difficult due to focusing problems, for instance.
Even though VS based on thick graded relaxed buffer layers can now be economically grown, e.g., by LEPECVD, the thick VS concept implies major disadvantages, such as                poor thermal conductivity, leading to problems with heat dissipation for SiGe devices, as mentioned above,        large surface roughness due to cross-hatch, requiring chemical mechanical polishing        problems with integration because of large step heights due to large SiGe layer thickness, as mentioned above.        
In the following, thin relaxed buffer layers serving as VS are addressed. In the past few years many attempts have been made to overcome the shortcomings of thick conventional graded buffers, aiming at a substantial reduction of buffer layer thickness to the range of 100-500 nm. In almost all cases these efforts have been carried out by means of solid source molecular beam epitaxy (MBE), which is not a suitable technique for large scale production. One notable exception is the work by K. K. Linder et al., who used gas-source molecular beam epitaxy and ultrahigh vacuum chemical vapor deposition. For details please refer to K. K. Under et al., Appl. Phys. Lett., Vol. 70, p. 3224, 1997. These processes are, however, extremely slow, of the order of a mono-layer per minute or less, at the low substrate temperatures required.
The most serious disadvantage of MBE is the limited capacity of the evaporation crucibles. This is a disadvantage in particular when growing SiGe-buffer layers having a thickness of up to 500 nm. MBE is thus not well suited for industrial production of devices comprising SiGe layers.
CVD processes in general, are not deemed to be suitable for deposition at low substrate temperatures even for VS thinner than ˜500 nm. In the “Handbook of thin-film deposition processes and techniques ed. Klaus. K. Schuegraf, Noyes Publications, New Jersey, USA, 1988, ISBN: 0-8155-1153-1, p. 26 through 79, there is an overview article by M. L. Hammond addressing Si epitaxy using CVD. It is clear from this article that there is an exponential decrease of the growth rate as the substrate temperature decreases. Estimates based on figures from various publications indicate that Si would grow at a rate between 0.01 nm/min and 0.0001 nm/min if using a CVD process at about 400° C. A SiGe alloy layer would probably grow at a rate that is certainly below 1 nm/min (0.0166 nm/s) if one were to use a CVD process at about 400° C.
One concept that was investigated is the deposition of a low temperature Si buffer before SiGe growth. The idea of this so-called low-temperature silicon (LT-Si) buffer was introduced by H. Chen et al., J. Appl. Phys., Vol. 79, p. 1167, 1995. Chen proposed a two-step growth process. It is based on the following premise: Silicon epitaxially grown at low substrate temperatures (typically of the order of 400° C.) contains a high concentration of point defects. These point defects may diffuse to the interface during subsequent SiGe growth at higher substrate temperature, and promote the nucleation of dislocation loops. Relaxation of the SiGe film therefore no longer requires formation of dislocation half-loops at the surface. Since the half-loops are associated always with two TDs, reducing their density should also reduce the density of TDs.
It is a disadvantage of this two-step growth process that it appears to fail at Ge concentrations x above ˜30%. It is, however, applicable to higher x if layers are grown in more than one step (cf. C. S. Peng et al., Appl. Phys. Lett., Vol. 72, p. 3160, 1998). Such a procedure is evidently time consuming.
Another two-step growth process starts with the epitaxial growth of SIGe at ultra-low temperatures. According to this concept, advocated by E. Kasper et al. in Thin Solid Films, Vol. 336, p. 319, 1998, it is the SiGe film itself which is grown in a first step at very low temperatures of the order of 200° C. by MBE. In a second step, the VS is completed by growing the film to its final thickness at a higher temperature (cf. M. Bauer et al. in Thin Solid Films Vol. 369, p. 152, 2000). The idea here is that point defects in the film should help dislocations with opposite Burgers vector to annihilate, because of dislocation climb. Furthermore, as in the case of LT-Si, condensation of point defects can result in the formation of dislocation loops inside the SiGe layer, avoiding dislocation nucleation from surface sites. It is a disadvantage of the concept advocated by E. Kasper et al., that it requires MBE.
Another approach is the post SiGe growth hydrogen ion Implantation or H-cleaning plus annealing. In this approach, described by S. Mantl et al. in Nucl. Instr. and Meth. in Phys. Res., Vol. B 147, p. 29, 1999, and by B. Holländer et al. in Nucl. Instr. and Meth. In Phys. Res., Vol. B 148, p. 200, 2000, hydrogen is implanted at some depth below the SiGe epilayer. In the subsequent annealing steps, micro cavities form which seem to promote the nucleation of dislocation loops. The latter can extend at the interface and act as misfit segments enabling strain relaxation.
An alternative method has been proposed by J. Kuchenbecker et al. in Thin Solid Films, Vol. 389, p. 146, 2001. In this paper, the Si wafer is exposed to a low-energy hydrogen plasma, and annealed for a short time, before the epitaxial growth of the SiGe layer by MBE. Similar to H-implantation, this process induces cavities below the interface, which again promote relaxation of the SiGe film upon annealing.
It is regarded as a disadvantage of these approaches, that for growth in one single step, Ge concentrations in the VS appear to be limited to approximately 20%.
Another approach—which is essentially similar to the previous one—is referred to as post SiGe growth helium ion implantation plus annealing. It differs from the previous approach in that the implanted species is He rather than H. It has, however, been shown to work up to Ge concentrations of 30% (cf. B. Holländer et al., Nucl. Instr. and Meth. In Phys. Res. B 175-177, p. 357, 2001). Transistor data obtained on 95 nm thick Si0.69Ge0.31 VS are comparable to those obtained on conventional graded VS (cf. H.-J. Herzog et al., IEEE Electron Device Letters, Vol. 23, p. 485, 2002.
VS growth by hydrogen and He implantation plus annealing could be used in industrial production, provided that the SiGe layers are grown by a gas phase process rather than by MBE, as In all publications mentioned above.
As addressed above, several approaches have been suggested and implemented to decrease the thickness of the VS to below ˜500 nm. While partially successful from a scientific point of view, all these approaches rely for the most part on processes unsuitable for large scale production.
It is a disadvantage of the known CVD approaches that the growth rate is low. Since a certain minimum thickness of ˜100 nm of the semiconductor layer (e.g., a SiGe VS) is required, the formation of this layer takes quite some time when using conventional approaches. This is, however, highly unfavorable for industrial mass production.
It is an object of the present invention to provide a method for making thin, highly relaxed semiconductor layers using processes suitable for large scale production.
It is an object of the present invention to provide a method for making SiGe layer(s) having a high degree of relaxation.
It is an object of the present invention to provide heterostructure devices made by such methods.